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CY7C1370CV25 CY7C1372CV25
512K x 36/1M x 18 Pipelined SRAM with NoBLTM Architecture
Features
* Pin-compatible and functionally equivalent to ZBTTM * Supports 250-MHz bus operations with zero wait states -- Available speed grades are 250, 225, 200 and 167 MHz * Internally self-timed output buffer control to eliminate the need to use asynchronous OE * Fully registered (inputs and outputs) for pipelined operation * Byte Write capability * Single 2.5V power supply * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 2.8 ns (for 225-MHz device) -- 3.0 ns (for 200-MHz device) -- 3.4 ns (for 167-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Available in 100 TQFP, 119 BGA, and 165 fBGA packages * IEEE 1149.1 JTAG Boundary Scan * Burst capability--linear or interleaved burst order * "ZZ" Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus LatencyTM (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370CV25 and CY7C1372CV25 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa-BWd for CY7C1370CV25 and BWa-BWb for CY7C1372CV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Logic Block Diagram-CY7C1370CV25 (512K x 36)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
C
WRITE ADDRESS REGISTER 1
WRITE ADDRESS REGISTER 2
ADV/LD
BWa BWb BWc BWd
WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
DQs DQPa DQPb DQPc DQPd
E
INPUT REGISTER 1
E
INPUT REGISTER 0
E
OE CE1 CE2 CE3
ZZ
READ LOGIC
SLEEP CONTROL
Cypress Semiconductor Corporation Document #: 38-05235 Rev. *C
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3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised June 03, 2004
CY7C1370CV25 CY7C1372CV25
Logic Block Diagram-CY7C1372CV25 (1M x 18)
A0, A1, A MODE CLK CEN C
WRITE ADDRESS REGISTER 1
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 2
ADV/LD BWa BWb WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
DQs DQPa DQPb
E
E
INPUT REGISTER 1 E
INPUT REGISTER 0 E
OE CE1 CE2 CE3 ZZ
READ LOGIC
Sleep Control
Selection Guide
CY7C1370CV25-250 CY7C1370CV25-225 CY7C1370CV25-200 CY7C1370CV25-167 CY7C1372CV25-250 CY7C1372CV25-225 CY7C1372CV25-200 CY7C1372CV25-167 Unit Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 350 70 2.8 325 70 3.0 300 70 3.4 275 70 ns mA mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05235 Rev. *C
Page 2 of 27
CY7C1370CV25 CY7C1372CV25
Pin Configurations
100-pin TQFP Packages
A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A
A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A
NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ V DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC
DDQ
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ
VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1370CV25 (512K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CY7C1372CV25 (1M x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0
E(288) E(144)
VSS VDD
E(36)
A A A A A A A
MODE A A A A A1 A0
E(72)
E(288) E(144)
E(72)
VSS VDD
Document #: 38-05235 Rev. *C
E(36)
A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 27
CY7C1370CV25 CY7C1372CV25
Pin Configurations (continued)
119-ball BGA Pinout CY7C1370CV25 (512K x 36) - 14 x 22 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ
2
A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A E(72) TMS
3
A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI
4
A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK
5
A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO
6
A CE3 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A E(36) NC
7
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
CY7C1372CV25 (1M x 18)-14 x 22 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC E(72) VDDQ
2
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS
3
A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI
4
A ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD E(36) TCK
5
A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO
6
A CE3 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
Document #: 38-05235 Rev. *C
Page 4 of 27
CY7C1370CV25 CY7C1372CV25
Pin Configurations (continued)
165-Ball fBGA Pinout
1 A B C D E F G H J K L M N P R
E(288) NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE
2
A A NC DQc DQc DQc DQc NC / VDD DQd DQd DQd DQd NC E(72) E(36)
CY7C1370CV25 (512K x 36) - 13 x 15 fBGA 3 4 5 6 7 8
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
9
A
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC E(144) DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
CE3 CLK
CEN WE
ADV/LD
OE
A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
CY7C1372CV25 (1M x 18) - 13 x 15 fBGA
1 A B C D E F G H J K L M N P R
E(288) NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE
2
A A NC DQb DQb DQb DQb NC / VDD NC NC NC NC NC E(72) E(36)
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE VSS VSS
8
ADV/LD
9
A
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A E(144) DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
OE VSS
A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
A
A
Document #: 38-05235 Rev. *C
Page 5 of 27
CY7C1370CV25 CY7C1372CV25
Pin Definitions
Name A0, A1, A BWa, BWb BWc, BWd WE ADV/LD I/O Type InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Pin Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa-DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.
CLK CE1 CE2 CE3 OE
CEN
InputSynchronous I/OSynchronous
DQa DQb DQc DQd
DQPa, DQPb DQPc, DQPd MODE
I/OSynchronous Input Strap Pin
TDO TDI TMS TCK VDD VDDQ VSS NC NC / VDD
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous JTAG-Clock Power Supply Ground - - Clock input to the JTAG circuitry. Power supply inputs to the core of the device. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. Can either be left unconnected or connected to VDD. Must not be connected to VSS. Page 6 of 27
I/O Power Supply Power supply for the I/O circuitry.
Document #: 38-05235 Rev. *C
CY7C1370CV25 CY7C1372CV25
Pin Definitions (continued)
Name E(36,72, 144, 288) ZZ I/O Type - InputAsynchronous Pin Description These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and 288M densities. ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. Burst Read Accesses The CY7C1370CV25 and CY7C1372CV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0-A16 is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370CV25 and DQa,b/DQPa,b for CY7C1372CV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1370CV25 & DQa,b/DQPa,b for CY7C1372CV25) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW (BWa,b,c,d for CY7C1370CV25 and BWa,b for CY7C1372CV25) signals. The CY7C1370CV25/ CY7C1372CV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1370CV25 and CY7C1372CV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP Page 7 of 27
Functional Overview
The CY7C1370CV25 and CY7C1372CV25 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (200-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[a:d] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.2 ns (200-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.
Document #: 38-05235 Rev. *C
CY7C1370CV25 CY7C1372CV25
(DQa,b,c,d/DQPa,b,c,d for CY7C1370CV25 and DQa,b/DQPa,b for CY7C1372CV25) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/ DQPa,b,c,d for CY7C1370CV25 and DQa,b/DQPa,b for CY7C1372CV25) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1370CV25/CY7C1372CV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1370CV25 and BWa,b for CY7C1372CV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1,A0 00 01 10 11 First Address A1,A0 00 01 10 11 Second Address A1,A0 01 00 11 10 Second Address A1,A0 01 10 11 00 Third Address A1,A0 10 11 00 01 Third Address A1,A0 10 11 00 01 Fourth Address A1,A0 11 10 01 00 Fourth Address A1,A0 11 00 01 10
Linear Burst Address Table (MODE = GND)
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max 60 2tCYC 2tCYC 0 Unit mA ns ns ns ns
2tCYC
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE Address Used None None External Next External Next External Next None Next Current None CE H X L X L X L X L X X X ZZ L L L L L L L L L L L H ADV/LD L H L H L H L H L H X X WE X X H X H X L X L X X X BWx X X X X X X L L H H X X OE X X L L H H X X X X X X CEN L L L L L L L L L L H X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X DQ Three-State Three-State Data Out (Q) Data Out (Q) Three-State Three-State Data In (D) Data In (D) Three-State Three-State - Three-State
Notes: 1. X = "Don't Care", 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQP[a:d] = Three-state when OE is inactive or when the device is deselected, and DQs=data when OE is active.
Document #: 38-05235 Rev. *C
Page 8 of 27
CY7C1370CV25 CY7C1372CV25
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1370CV25) Read Write - No bytes written Write Byte a - (DQa and DQPa) Write Byte b - (DQb and DQPb) Write Bytes b, a Write Byte c - (DQc and DQPc) Write Bytes c, a Write Bytes c, b Write Bytes c, b, a Write Byte d - (DQd and DQPd) Write Bytes d, a Write Bytes d, b Write Bytes d, b, a Write Bytes d, c Write Bytes d, c, a Write Bytes d, c, b Write All Bytes Function (CY7C1372CV25) Read Write - No Bytes Written Write Byte a - (DQa and DQPa) Write Byte b - (DQb and DQPb) Write Both Bytes WE H L L L L L L L L L L L L L L L L BWd X H H H H H H H H L L L L L L L L WE H L L L L Test Access Port-Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. BWc X H H H H L L LL L H H H H L L L L BWb x H H L L BWb X H H L L H H L L H H L L H H L L BWa X H L H L H L H L H L H L H L H L BWa x H L H L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370CV25/CY7C1372CV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.
Note: 8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.
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Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 69-bit-long register, and the x18 configuration has a 69-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. Page 10 of 27
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When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 1
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0
1
SELECT IR-SCAN 0 1 CAPTURE-DR 0
0
SHIFT-IR 1
0
1
EXIT1-IR 0
1
0
PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP Controller Block Diagram
0 Bypass Register Selection Circuitry TDI 31 30 2 Instruction Register 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 68 . . . . 2 1 0
Boundary Scan Register
TCK TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[10, 11]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Input Load Current TMS and TDI GND VI VDDQ GND VI VDDQ IOH = -1.0 mA IOH = -100 A IOL = 1.0 mA IOL = 100 A Test Conditions VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V 1.7 -0.3 -5 -5 Min. 1.7 2.1 0.4 0.2 VDD + 0.3 0.7 5 5 Max. Unit V V V V V V A A
TAP AC Switching Characteristics Over the Operating Range [12, 13]
Parameter tTCYC tTF tTH tTL tTMSS tTDIS tCS Hold Times tTMSH TMS Hold after TCK Clock Rise 10 ns
Notes: 10. All voltage referenced to ground. 11. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) > -0.5V for t < tTCYC/2. 12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Description TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise
Min. 100
Max. 10
Unit ns MHz ns ns ns ns ns
40 40 10 10 10
Set-up Times
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TAP AC Switching Characteristics Over the Operating Range [12, 13] (continued)
Parameter tTDIH tCH tTDOV tTDOX TDI Hold after Clock Rise Capture Hold after clock rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 Description Min. 10 10 20 Max. Unit ns ns ns ns
Output Times
TAP Timing and Test Conditions
1.25V for 2.5V VDDQ 50 TDO Z0 = 50 CL = 20 pF VSS 1.5 ns ALL INPUT PULSES 2.5V 1.25V 1.5 ns
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOV tTDOX
Identification Register Definitions
Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) CY7C1370CV25 010 01011001000100101 00000110100 1 CY7C1372CV25 010 00000110100 1 Description Reserved for version number. Allows unique identification of SRAM vendor. Indicate the presence of an ID register.
01011001000010101 Reserved for future use.
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Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size(x18) 3 1 32 70 Bit Size (x36) 3 1 32 70
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED Code 000 001 010 011 Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE/PRELOAD 100
RESERVED RESERVED BYPASS
101 110 111
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119-ball BGA Boundary Scan Order
CY7C1370CV25 (512K x 36) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Ball ID K4 H4 M4 F4 B4 A4 G4 C6 A6 D6 D7 E6 G6 H7 E7 F6 G7 H6 T7 K7 L6 N6 P7 K6 L7 M6 N7 P6 B5 B3 C5 C3 C2 A2 T4 Bit# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Ball ID P4 N4 R6 T5 T3 R2 R3 P2 P1 N2 L2 K1 N1 M2 L1 K2 Not Bonded (Preset to 1) H1 G2 E2 D1 H2 G1 F2 E1 D2 A5 A3 E4 B2 L3 G3 G5 L5 B6 Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 CY7C1372CV25 (1M x 18) Ball ID K4 H4 M4 F4 B4 A4 G4 C6 A6 T6 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) D6 E7 F6 G7 H6 T7 K7 L6 N6 P7 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) B5 B3 C5 C3 C2 A2 T2 Bit# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Ball ID P4 N4 R6 T5 T3 R2 R3 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) P2 N1 M2 L1 K2 Not Bonded (Preset to 1) H1 G2 E2 D1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) A5 A3 E4 B2 Not Bonded (Preset to 0) G3 Not Bonded (Preset to 0) L5 B6
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165-Ball fBGA Boundary Scan Order
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 CY7C1370CV25 (512K x 36) Ball Id Bit# Ball Id B6 36 R6 B7 37 P6 A7 38 R4 B8 39 R3 A8 40 P4 B9 41 P3 A9 42 R1 B10 43 N1 A10 44 L2 C11 45 K2 E10 46 J2 F10 47 M2 G10 48 M1 D10 49 L1 D11 50 K1 E11 51 J1 F11 52 Not Bonded (Preset to 1) G11 53 G2 H11 54 F2 J10 55 E2 K10 56 D2 L10 57 G1 M10 58 F1 J11 59 E1 K11 60 D1 L11 61 C1 M11 62 A2 N11 63 B2 R11 64 A3 R10 65 B3 R9 66 B4 R8 67 A4 P10 68 A5 P9 69 B5 P8 70 A6 Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 CY7C1372CV25 (1M x 18) Ball ID Bit# Ball ID B6 36 R6 B7 37 P6 A7 38 R4 B8 A8 B9 A9 B10 A10 A11 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) D11 E11 F11 G11 H11 J10 K10 L10 M10 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) R11 R10 R9 R8 P10 P9 P8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 R3 P4 P3 R1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) N1 M1 L1 K1 J1 Not Bonded (Preset to 1) G2 F2 E2 D2 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) A2 B2 A3 B3 Not Bonded (Preset to 0) Not Bonded (Preset to 0) A4 B5 A6
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC to Outputs in Tri-State ................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C VDD VDDQ
2.5V-5%/+5% 2.5V -5% to VDD -40C to +85C
Electrical Characteristics Over the Operating Range[14, 15]
Parameter VDD VDDQ VOH VOL VIH VIL IX IOZ IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[14] Input Load Current Input Current of MODE Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4.0-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB1 Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz VIN VIH or VIN VIL, f = fMAX = 4.4-ns cycle, 225 MHz 1/tCYC 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB2 ISB3 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 Automatic CE Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz Power-down VIN 0.3V or VIN > VDDQ - 0.3V, 4.4-ns cycle, 225 MHz Current--CMOS Inputs f = fMAX = 1/tCYC 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz ISB4 Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = 0 All speed grades VDDQ = 2.5V VDD = Min., IOL= -1.0 mA, VDDQ = 2.5V VDD = Min., IOL= 1.0 mA, VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V GND VI VDDQ 1.7 -0.3 -5 -30 -5 Test Conditions Min. 2.375 2.375 2.0 0.4 VDD + 0.3V 0.7 5 30 5 350 325 300 275 120 110 100 90 70 105 100 95 85 80 Max. 2.625 VDD Unit V V V V V V A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Shaded areas contain advance information. Notes: 14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 15. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance[16]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance
R=1667 ALL INPUT PULSES VDD 0V R = 1538 90% 10% < 1.0 ns 1.25V
Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V
BGA Max. 8 8 8
fBGA Max. 9 9 9
TQFP Max. 5 5 5
Unit pF pF pF
AC Test Loads and Waveforms
OUTPUT Z0 = 50 RL = 50 VL = 1.25V 2.5V Output 5 pF INCLUDING JIG AND SCOPE
[16]
90% 10% < 1.0 ns
(a)
(b)
(c)
Thermal Resistance[16]
Parameters QJA QJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51.
[ 21, 22]
BGA Typ. 45 7
fBGA Typ. 46 3
TQFP Typ. 31 6
Unit C/W C/W
Notes 17 17
Switching Characteristics Over the Operating Range
Parameter tPower Clock tCYC FMAX tCH tCL Output Times tCO tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Set-up Times tAS tDS
[17]
Description VCC (typical) to the first access read or write Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW Data Output Valid After CLK Rise OE LOW to Output Valid Data Output Hold After CLK Rise Clock to High-Z[18, 19, 20] Clock to Low-Z[18, 19, 20] OE HIGH to Output High-Z[18, 19, 20] OE LOW to Output Low-Z[18, 19, 20] Address Set-up Before CLK Rise Data Input Set-up Before CLK Rise
-250 Min. Max. 1 4.0 250 1.7 1.7 2.6 2.6 1.0 2.6 1.0 2.6 0 1.2 1.2
-225 Min. Max. 1 4.4 225 2.0 2.0 2.8 2.8 1.0 2.8 1.0 2.8 0 1.4 1.4
-200 -167 Min. Max. Min. Max. 1 5 200 2.0 2.0 3.0 3.0 1.3 3.0 1.3 3.0 0 1.4 1.4 0 1.5 1.5 1.3 3.4 1.3 3.4 2.2 2.2 3.4 3.4 1 6 166
Unit ms ns MHz ns ns ns ns ns ns ns ns ns ns ns
Shaded areas contain advance information. Notes: 16. Tested initially and after any design or process changes that may affect these parameters. 17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be initiated. 18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. 21. Timing reference is 1.25V when VDDQ=2.5V. 22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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Switching Characteristics Over the Operating Range (continued)[ 21, 22]
Parameter tCENS tWES tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Description CEN Set-up Before CLK Rise WE, BWx Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise Chip Select Set-up Address Hold After CLK Rise Data Input Hold After CLK Rise CEN Hold After CLK Rise WE, BWx Hold After CLK Rise ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise -250 Min. Max. 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 -225 Min. Max. 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 -200 -167 Min. Max. Min. Max. 1.4 1.5 1.4 1.5 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Unit ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Read/Write/Timing[23,24,25] 1
2
t CYC
3
4
5
6
7
8
9
10
CLK
tCENS tCENH tCH tCL
CEN
tCES tCEH
CE ADV/LD WE BWx ADDRESS
tAS
A1
tAH
A2
tDS tDH
A3
A4
tCO tCLZ tDOH
A5
tOEV
A6
tCHZ
A7
Data In-Out (DQ)
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
tOEHZ
Q(A4+1)
D(A5)
Q(A6)
tDOH
OE
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5)
tOELZ
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
Notes: 23. For this waveform ZZ is tied low. 24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
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CY7C1370CV25 CY7C1372CV25
Switching Waveforms (continued)
NOP,STALL AND DESELECT Cycles[23,24,26]
1
CLK CEN CE ADV/LD WE BWx ADDRESS A1
2
3
4
5
6
7
8
9
10
A2
A3
A4
A5
tCHZ
Data In-Out (DQ)
WRITE D(A1) READ Q(A2) STALL
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
READ Q(A3)
WRITE D(A4)
STALL
NOP
READ Q(A5)
DESELECT
CONTINUE DESELECT
DON'T CARE
UNDEFINED
ZZ Mode Timing[27,28]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05235 Rev. *C
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CY7C1370CV25 CY7C1372CV25
Ordering Information
Speed (MHz) 250 Ordering Code CY7C1370CV25-250AC CY7C1372CV25-250AC CY7C1370CV25-250BGC CY7C1372CV25-250BGC CY7C1370CV25-250BZC CY7C1372CV25-250BZC 225 CY7C1370CV25-225AC CY7C1372CV25-225AC CY7C1370CV25-225BGC CY7C1372CV25-225BGC CY7C1370CV25-225BZC CY7C1372CV25-225BZC 200 CY7C1370CV25-200AC CY7C1372CV25-200AC CY7C1370CV25-200BGC CY7C1372CV25-200BGC CY7C1370CV25-200BZC CY7C1372CV25-200BZC 167 CY7C1370CV25-167AC CY7C1372CV25-167AC CY7C1370CV25-167BGC CY7C1372CV25-167BGC CY7C1370CV25-167BZC CY7C1372CV25-167BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Package Name A101 Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Operating Range Commercial
Document #: 38-05235 Rev. *C
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CY7C1370CV25 CY7C1372CV25
Ordering Information (continued)
Speed (MHz) 250 Ordering Code CY7C1370CV25-250AI CY7C1372CV25-250AI CY7C1370CV25-250BGI CY7C1372CV25-250BGI CY7C1370CV25-250BZI CY7C1372CV25-250BZI 225 CY7C1370CV25-225AI CY7C1372CV25-225AI CY7C1370CV25-225BGI CY7C1372CV25-225BGI CY7C1370CV25-225BZI CY7C1372CV25-225BZI 200 CY7C1370CV25-200AI CY7C1372CV25-200AI CY7C1370CV25-200BGI CY7C1372CV25-200BGI CY7C1370CV25-200BZI CY7C1372CV25-200BZI 167 CY7C1370CV25-167AI CY7C1372CV25-167AI CY7C1370CV25-167BGI CY7C1372CV25-167BGI CY7C1370CV25-167BZI CY7C1372CV25-167BZI
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Package Name A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A A101 BG119 BB165A
Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm)
Operating Range Industrial
Document #: 38-05235 Rev. *C
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CY7C1370CV25 CY7C1372CV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
16.000.20 14.000.10
100 1 81 80
DIMENSIONS ARE IN MILLIMETERS.
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX.
0.10
R 0.08 MIN. 0.20 MAX.
0 MIN.
0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX.
SEATING PLANE
0-7 0.600.15
0.20 MIN. 1.00 REF.
DETAIL
A
51-85050-*A
Document #: 38-05235 Rev. *C
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CY7C1370CV25 CY7C1372CV25
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05235 Rev. *C
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CY7C1370CV25 CY7C1372CV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-05235 Rev. *C
Page 26 of 27
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1370CV25 CY7C1372CV25
Document History Page
Document Title: CY7C1370CV25/CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBLTM Architecture Document Number: 38-05235 REV. ** *A *B *C ECN No. 116273 121536 206100 231349 Issue Date 08/27/02 11/21/02 see ECN See ECN Orig. of Change SKX DSG RKF DIM New Data Sheet Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev. *C Final Data Sheet Pin H2 (165 fBGA) changed from NC to NC/VDD. Updated ordering information: unshade active parts. Description of Change
Document #: 38-05235 Rev. *C
Page 27 of 27

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